For switching mode power converters the output voltage is controlled by an electronic circuit which measures a level of electric current within the circuit, compares that measured level to a predetermined desired level, and develops a response to that measurement elsewhere in the circuit in order to more accurately achieve the desired level. A switching mode power converter which uses a trailing edge modulation control scheme is illustrated in FIG. 1. The input voltage VIN is coupled to a first terminal of the inductor L1. A second terminal of the inductor L1 is coupled to a first terminal of the switch SW1 and to the anode of the diode SW2. A capacitor C1 is coupled between the cathode of the diode SW2 and a second terminal of the switch SW1. A load RL is coupled across the capacitor C1. A potentiometer PT1 is coupled across the load RL and provides a negative input to a voltage error amplifier 10. A reference voltage REF is coupled to the positive input of the error amplifier 10. The output VEAO of the voltage error amplifier 10 is coupled as the positive input of a modulating comparator 14. The negative input of the modulating comparator 14 is coupled to receive the ramp output of an oscillator 12. The output of the modulating comparator 14 is coupled as the reset input R of a flip flop 16. The input D of the flip flop 16 is coupled to the inverted output Q of the flip flop 16. A clock input CLK of the flip flop 16 is coupled to the clock output of the oscillator 12. The output Q of the flip flop 16 is coupled to control the operation of the switch SW1.
The output voltage VOUT is established by integrating the inductor current I1 in the LC filter network. This integrated current is supplied to the load circuit as the converted output voltage VOUT. In order to establish the proper output voltage from a given input voltage, the input voltage VIN is switched in and out of the circuit by the switch SW1. The resulting oscillating signal is integrated in the LC network to form the desired output voltage VOUT. If the input voltage VIN changes or varies over time, the frequency at which the switch SW1 is opened and closed can also be varied in order to maintain the desired output voltage VOUT.
Pulse width modulation (PWM) is a technique used to maintain a constant output voltage VOUT when the input voltage does not remain constant and varies over time. By changing the frequency at which the switch SW1 is opened and closed, as the input voltage changes, the output voltage VOUT can be maintained at a constant level as desired. The inductor current I1 is stored as a voltage level on the plates of the capacitor C1 when the switch SW1 is open. Because of its parallel connection to the output of the circuit, the voltage across the capacitor C1 is equivalent to the output voltage VOUT and the voltage across the potentiometer PT1. A predetermined fraction of that voltage is measured from the potentiometer PT1 forming the voltage VEA which is input into the negative terminal of the voltage error amplifier 10 and is compared to the reference voltage REF. This comparison determines how close the actual output voltage VOUT is to the desired output voltage.
Conventional pulse width modulation techniques use the trailing edge of the clock signal, so that the switch will turn on right after the trailing edge of the system clock. FIG. 1 illustrates such a trailing edge modulation control scheme. The leading edge of the clock signal may also be used for pulse width modulation. In order to implement a leading edge modulation control scheme the inputs to the error amplifier 10 must be reversed: the voltage VEA from the potentiometer PT1 is coupled to the positive terminal of the voltage error amplifier 10 and the reference voltage REF is coupled to the negative terminal of the voltage error amplifier 10.
FIGS. 2, 3 and 4 show corresponding voltage waveforms with respect to time of different voltage levels at different points within the switch control circuitry 31 of the trailing edge scheme. The time axis for the FIGS. 2, 3 and 4 has been drawn to correspond in all three figures. FIG. 2 illustrates the voltage levels with respect to time of the error amplifier output VEAO and the modulating ramp output of the oscillator 12. FIG. 3 illustrates the voltage level of the control voltage VSW1 for the switch SW1 with respect to time. The switch SW1 is "on" or closed when the control voltage VSW1 is at a high voltage level. The switch SW1 is "off" or open when the control voltage is at a low voltage level. FIG. 4 illustrates the clock impulses with respect to time of the clock output of the oscillator 12.
The switch SW1 will turn on after the trailing edge of the system clock. Once the switch SW1 is on, the modulating comparator 14 then compares the error amplifier output voltage VEAO and the modulating ramp. When the modulating ramp reaches the error amplifier output voltage, the output of the modulating comparator 14 will fall to a logical low voltage level. Because of the inverter coupled to the input, the input R of the flip flop 16 will then rise to a logical high voltage level thereby resetting the output Q of the flip flop 16 to a logical low voltage level and turning the switch SW1 off. When the switch SW1 is on, the inductor current IL will ramp up. The effective duty cycle of the trailing edge modulation is determined during the on time of the switch. FIG. 1 illustrates a typical trailing edge control scheme using a single boost power converter stage. As the input voltage VIN varies over time, the duty cycle or time that the switch SW1 is on will vary in order to maintain a constant output voltage VOUT.
A more detailed circuit diagram of a power factor controller circuit is illustrated in FIG. 5. Elements that are identical to those of FIG. 1 use the same reference numerals. The line voltage is coupled to the input terminals 20 and 22. The input terminals 20 and 22 are coupled across a full wave bridge rectifier 28. The full wave bridge rectifier 28 is also coupled to provide the DC input signal to the inductor L1. The output of the voltage error amplifier 10 is coupled as an input to a multiplier 30. A first terminal of a reference resistor R1 is coupled to the first terminal of the inductor L1. A second terminal of the resistor R1 is coupled as an input to the multiplier 30. The output of the multiplier 30 is coupled to a positive input terminal of a current error amplifier 32 and to a first terminal of a resistor RC. A second terminal of the resistor RC is coupled to the full wave bridge rectifier 28 and to a first terminal of a sense resistor RS. A second terminal of the sense resistor RS is coupled to the output terminal 26, to a first terminal of a resistor RCI and to ground. A second terminal of the resistor RCI is coupled to a negative input terminal of the current error amplifier 32. The output of the current error amplifier 32 is coupled to the negative input terminal of the modulating comparator 14 and as a feedback to the negative input terminal of the current error amplifier 32. The ramp output of the oscillator 12 is coupled to the positive input terminal of the modulating comparator 14. The output of the modulating comparator 14 is coupled as an input R of a flip flop 16. The clock output of the oscillator 12 is coupled as an input S of the flip flop 16. The output Q of the flip flop 16 is coupled to the gate of the switch SW1. In the circuit illustrated in FIG. 5 a MOSFET is used as the switch SW1.
The function of the power factor correction section is to ensure that the current follows the voltage in time and amplitude proportionally. A reference current that is proportional to the input full wave rectified voltage is produced with the help of the reference resistor R1. The reference current is applied to one of the inputs of the multiplier 30. The other input of the multiplier 30 is the output of the voltage error amplifier 10. The multiplier 30 is usually of a current input type which enables the multiplier 30 to have greater ground noise immunity. When there is a current at its input, the terminal voltage of the multiplier 30 is a diode drop between 0.7 V and 1 V.
The output of the multiplier 30 is a current which is the product of the reference current, the output of the voltage error amplifier 10 and a gain adjustor factor which will be described below. This output current is applied to the resistor RC. The voltage across the resistor RC subtracts from the sensed voltage across the sense resistor RS and is applied to the current error amplifier 32. Under closed loop control the current error amplifier 32 will try to keep this voltage differential near the zero volt level. This forces the voltage produced by the return current flowing through the sense resistor RS to be equal to the voltage across the resistor RC.
The amplified current error signal output from the current error amplifier 32 is then applied to the inverting input of the modulating comparator 14. The other input of the modulating comparator 14 is coupled to receive the ramp signal output from the oscillator 12. Pulse width modulation is obtained when the amplified error signal that sets up the trip point modulates up and down.
A current control loop modulates the duty cycle of the switch SW1 in order to force the input current waveshape to follow the shape of the input voltage. The input voltage is a full wave rectified sinewave. The current control loop and the power delivery circuitry must have at least enough bandwidth to follow this full wave rectified waveform.
As the RMS input voltage increases, the gain of the system will increase by the voltage RMS value V.sub.RMS. The gain of the system will increase as the input voltage increases because the input to the multiplier 30 is driven by the input voltage through the reference resistor R1. The gain of the multiplier 30 can be adjusted as a function of the RMS input voltage in order to cancel the square law dependency of the signal. A graph of a typical gain adjustor gain for the multiplier 30 is illustrated in FIG. 6. The gain K of the multiplier 30 is curve fitted to a value equal to 1/(V.sub.RMS).sup.2 for universal input. For an a.c. input voltage less than 85 VAC the gain K starts brown out and will not fit the 1/(V.sub.RMS).sup.2 curve. Since the output of the multiplier 30 is dependent on the rectified sinusoidal input voltage, the output of the multiplier 30 is generated in phase with the sinusoidal line input voltage.
A schematic diagram of a basic dual comparator R-C relaxation oscillator 12 which is typically used to generate the clock and ramp reference signals used within the power factor correction circuit is illustrated in FIG. 7. This circuit consists of three functional subblocks: (i) the comparators X.sub.1 and X.sub.2 for detecting the threshold voltages V.sub.TH and V.sub.TL, set by the resistive divider network including the resistors R.sub.A, R.sub.B and R.sub.C ; (ii) the timing components including the resistor R.sub.T, the capacitor C.sub.T and the resistor R.sub.D ; and (iii) an R-S latch X.sub.3 for controlling the discharge of the capacitor C, through the npn transistor Q.sub.D and the resistor R.sub.D.
Assuming that the output Q of the R-S latch X.sub.3 is at a logical low and the transistor Q.sub.D is turned off initially, the resistor R.sub.T will charge the capacitor C.sub.T towards the upper threshold voltage V.sub.TH. The upper threshold voltage V.sub.TH is set by the resistive divider as ##EQU1##
The output of the comparator X.sub.1 rises from a logical low voltage level to a logical high voltage level when the voltage across the capacitor C.sub.T crosses the upper threshold voltage V.sub.TH and the positive input of the comparator X.sub.1 becomes greater than its negative input. Once the output of the comparator X.sub.1 switches to a logical high voltage level, the input S of the R-S latch X.sub.3 will also be raised to a logical high voltage level and the output Q of the R-S latch X.sub.3 will rise from a logical low voltage level to a logical high voltage level. The transistor Q.sub.D will then turn on and saturate. If the value of the resistor R.sub.D is properly chosen, the transistor Q.sub.D and the resistor R.sub.D will discharge the voltage across the capacitor C.sub.T towards the lower threshold voltage V.sub.TL set again by the resistive divider network as ##EQU2##
As the voltage across the capacitor C.sub.T is discharged below the upper threshold voltage V.sub.TH and the positive input of the comparator X.sub.1 becomes less than the negative input, the output of the comparator X.sub.1 will drop from a logical high voltage level to a logical low voltage level. When the voltage across the timing capacitor C.sub.T falls below the lower threshold voltage V.sub.TL so that the negative input of the comparator X.sub.2 is less than the positive input, the output of the comparator X.sub.2 will rise to a logical high voltage level and the R-S latch X.sub.3 will reset. When the R-S latch X.sub.3 is reset the output Q of the R-S latch will drop to a logical low voltage level turning the transistor Q.sub.T off and ending the discharge cycle. The resistor R.sub.T will then charge the timing capacitor C.sub.T and the cycle will repeat. The timing diagram of the oscillator of FIG. 7 is shown in FIG. 8. The ramp output is taken from the node formed between the timing resistor R.sub.T and the timing capacitor C.sub.T. The clock output is taken from the output Q of the R-S latch X.sub.3. In the oscillation circuits of the prior art the amplitude of the ramp output is fixed between the threshold values V.sub.TH and V.sub.TL. Within a power factor correction circuit, a fixed amplitude ramp signal causes the bandwidth of the current control loop to vary and also has a detrimental effect on the transient response of the circuit.
What is needed is a ramp reference signal with an amplitude which varies as the a.c. input signal varies, for use by the power factor correction controller. What is further needed is a synchronizing circuit which will synchronize the ramp reference signal to the clock reference signal.